This invention relates to a logic circuit, and more particularly to the dynamic testability of a programmable logic array.
In the design of logic circuits, programmable logic arrays (PLA) have become increasingly more important for designing combinational logic circuits. These programmable logic arrays offer a greater variety and flexibility in logic design while lowering parts count and inventory requirements, and are also proving to be very cost effective. With programmable logic devices, a designer can customize a reliable, high volume integrated circuit to fit a specific application, and quickly.
However, until recently, little has been done to test the programmable logic array in the unprogrammed state. This is due in part to the unavailability of an adequate number of test points on the chip. The various testing techniques devised require augmenting the PLA with a substantially large amount of additional logic which can interfere with the normal operation of the PLA logic or which requires and dissipates additional power even while the PLA is operating normally.
The related application of paragraph (a) above presents a novel approach for providing static (or dc) test capability of a programmable logic array in the unprogrammed state with some small amount of added logic which is inoperative and dissipates no added power while the PLA is operating in its normal environment.
Presently, ac, or dynamic, testing is either not performed or is performed after the programmable logic array is programmed. Thus, it is apparent that ac testing of programmed programmable logic arrays (or devices) require individualized test procedures or routines. Since many programmed combinations may be available, the number of individualized test routines can be quite high.
Hence, it would be highly desirable to ac test a programmable logic array in an unprogrammed state. The present invention presents a novel approach for providing dynamic (or ac) test capability of a programmable logic array in the unprogrammed state. Some additional circuit components are added to the test logic of the programmable logic array to provide the dynamic test capability without comprising the static test capability.